signal processing - How to use a DSP Slice in FPGAs (Artix7) -

I've recently started programming the FPGAs and I have to work with DSP slices onboard. I immediately went to copy the user's guide, but I do not know how to do part of its behavior. There is also code for a little work, but I know that please help me to combine them :( People I'm quite desperate ... btw I VHDL

  Library UNISIM use not; UNISIM use develloping use .vcomponents.all; library UNIMACRO; unimacro.Vcomponents.all; ADDMACC_MACRO_inst: ADDMACC_MACRO general map (device = & gt; "7SERIES", - the target device: "7SERIES", " VIRTEX6 "," SPARTAN6 "lATENCY = & gt; 4, - desired clock cycle latency, 1-4 WIDTH_PREADD = & gt; 25, - pre-adder input bus width, 1-25 WIDTH_MULTIPLIER = & gt; 18, - Unk input bus width, 1-18 WIDTH_PRODUCT = & gt; 48) - MACC production width, 1-48 port map (product = & gt; product, - MACC results produced, defined by the width WIDTH_PRODUCT general MULTIPLIER = & gt; multiplier, - multiple data input, WIDTH_MULTIPLIER width to be determined by the general PREADDER1 = & gt; PREADDER1, - Preadder data input, WIDTH_PREADDER general PREADDER2 = & width defined gt; PREADDER2, - Preadder data provide input, width WIDTH_PREADDER generic Kerinin = & gt ; Carinine, - 1-bit In-In Input CE = & gt; CE, - 1-bit input clock CLK = & gt; CLK, - 1-bit clock input LOAD = & gt; Load, - 1-bit accumulator load input LOAD_DATA = & gt; LOAD_DATA, - balloon load data input width that WIDTH_PRODUCT general RST = & gt; RST - 1-bit input active high synchronous reset); - ADDMACC_MACRO_inst instantiation end  

And there are some code I've written so far:

  unit test port (the clk: std_logic inout; oclk: out std_logic; end of the test, begins oclk practice of architecture test & lt; = clk not, start the process clk & lt; = '1'; 5 ns; clk and lt; = '0'; 5 for ns wait; end process; end behavior;